library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity CNT4 is
     Port ( CLK : in   STD_LOGIC;
            Q : out   STD_LOGIC_VECTOR (3 downto 0);
      fn:out std_logic_vector(1 downto 0);
      en:out std_logic_vector(1 downto 0));
end CNT4;

architecture Behavioral of CNT4 is
signal q1:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if CLK'event and CLK='1' then
q1<=q1+1;
end if;
end process;
Q<=q1;
fn<="10";
en<="00";
end Behavioral;