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learn marvel summury(转载)
2007/08/06 19:05
关键词switch    vlan    marvell                                           

1.if the ingressing frame's VID were 0x000,the Ingress port's DefaultVID(see Default Port
   VLAN ID and Priority register,offset 0x07) is assigned to the frame instead.


2.SMI:(serial management interface -MDC/MDIO).

3.laser   ¼¤¹⡣

4.what's TQFP package.

5.MDC:management Data Clock.

6.PPU:PHY Polling Unit.

7.MDIO:Management Data I/O.

8.This device support possible 32 SMI port addresses(two modes are supported).

9.The contents of the vlan database can be dumped or searched.

10.All DSA Tag frames are tagged,this bit is used to inform the egress port to consider
    this frame as tagged   so it will be transmitted as tagged.

11.The CFI bit in From_CPU DSA Tag frames is placed at b15.When this frame egresses out
    a normal network port the CFI bit will be moved to its correct position at b12.

12.trg_dev: Target Device.These bits are used to define the target device's number.
    use 0x00 for signal chip switches.   use non-zero value for multi chip cascaded switches.

13.cascade 瀑布,层叠式的。    

14.hierarchical 分等级的

15.DBNum:   Database Number.

16.SPID: The source port id. These bits indicate at which physical port the frame
    entered   this device(ti is assigned by the last physical device this frame enterd).
   
17.IMS:Ingress Monitor Source.
    EMS:Egress Monitor Source.  
   
18.latch:插门匙

19.we access the register via smi command register's devaddr and regaddr bits to
    point to the devices register to access.
    of courese we can use devaddr and regaddr values defined for devices in the
    single-chip addressing mode.
   
20.in this gemini we must work in single-chip addressing mode.

21.each ethernet port in the devices contain their own per port registers.

22.in port register,there is a DSA_Tag : when this bit is set to a one,it indicates this
    this port is a interswitch port used to communicated with a CPU or to cascade with
    another switch device.Frames egressing this port are modified with the DSA Tag and
    frame ingressing this port are expected to always contain a DSA Tag.Of coure,when
    this bit is cleared to a zero it indicates this port is a normal network port and
    DSA Tags are not used.

23.tunnel :隧道。

24.manipulate:熟练,操练,使用

25.the device contains four physical layer devices.
    these devices are accessible using SMI device addresses 0x00 to 0x07 depending
    upon the value of the pins at reset.

26.MII:Media Independent Interface.
   MII (Media Independent Interface )是介质无关接口。40针。
  
27.GMII:吉比特媒体独立接口是一种以太网接口,简称GMII(Gigabit Media Independent Interface)
    ...PCI9054芯片是目前主流的PCI总线接口芯片之一。  

28.In reverse MII mode initially,the link status is down requring the system software to force
    the port's link up to enable the port.
   
29.so port 9 and port 10 skiped by phy polling unit.

30.throttle:扼杀。   

31.VTP:vlan trunk protocl.

32.jabber.闲聊。

33.retain 保留

34.stretch   伸展 延长

35.thermal    热的,热量的

36.disspation   消散,分散,消失

37.PCS: what is pcs? It's means physical coding sublayers!

38.scrambler: 爬行者,扰频器

39.What is PMD: It's means physical media dependent sublayer!

40.MDI: Media dependent interface!

41.consectutive   连续的。连贯的

42.VCT: Vitual cavle tester feature!

43.copper line loopback:line loopback allows a link partner to send frames into the
    device to test the transmit and receive data path.
    so, before enbling the line loopback feature, the phy must first establish link to
    another phy link partner.
   
44.the device registers are accesssible using the mdc   

45.switch registers
    45.1   Table51 register map-multi-chip   addressing mode.
    45.2   Table52 register map-single-chip addressing mode.
          switch per-port registers:32bits.
          switch global registers:   32bits.
          switch global 2 registers:32bits.
         
         
          the registers in the devices are madu up of one or more fields.
         
          RWR:After reset,register field is cleared to zero.
          RWS:After reset,register field is set tp non-zero value specified in the text.
         
46.An SMI address of 0x00 is not supported in mult-chip mode as this value on the
    ADDR[4:0] pins places the device into signal-chip addressing mode.
   
47.SMI Command Register 16 bits.
    SMIOP
   
48.in gloable register,there is a diffaddr .
    this bit is used to have all ports transmit the same or different source addresses
    in full-duplex pause frames.

【作者: amoid】【访问统计: 37】【2006年02月9日 星期四 14:50】【 加入博采】【打印

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